Id-dar > Aħbarijiet > Il-kontenut

FT_Gpu_Hal.cpp

May 06, 2019

#inkludi "FT_Platform.h"



/ * API biex tibda l-interface SPI * /

ft_bool_t Ft_Gpu_Hal_Init (Ft_Gpu_HalInit_t * halinit)

{

#ifdef ARDUINO_PLATFORM_SPI

pinMode (FT_ARDUINO_PRO_SPI_CS, OUTPUT);

pinMode (FT800_PD_N, OUTPUT);

digitalWrite (FT_ARDUINO_PRO_SPI_CS, GĦOLJA);

DigitalWrite (FT800_PD_N, GĦOLJA);

#endif

#ifdef MSVC_PLATFORM_SPI

/ * Inizjalizza l-libmpsse * /

Init_libMPSSE ();

SPI_GetNumChannels (& halinit-> TotalChannelNum);

/ * Konvenzjonalment qed nassumi li kejbil wieħed biss tal-mpsse huwa mqabbad mal-PC u l-kanal 0 ta 'dak il-kejbil mpsse jintuża għal transazzjonijiet spi * /

jekk (halinit-> TotalChannelNum> 0)

{

FT_DEVICE_LIST_INFO_NODE devList;

SPI_GetChannelInfo (0, & devList);

printf ("Informazzjoni dwar in-numru tal-kanal% d:", 0);

/ * Ipprintja l-informazzjoni dwar l-iżvilupp * /

printf ("bnadar = 0x% x", devList.Flags);

printf ("Tip = 0x% x", devList.Type);

printf ("ID = 0x% x", devList.ID);

printf ("LocId = 0x% x", devList.LocId);

printf ("SerialNumber =% s", devList.SerialNumber);

printf ("Deskrizzjoni =% s", devList.Description);

printf ("ftHandle = 0x% x", devList.ftHandle); / * huwa 0 sakemm mhux miftuħ * /

}

#endif

ritorn VERU;

}

ft_bool_t Ft_Gpu_Hal_Open (Ft_Gpu_Hal_Context_t * host)

{

#ifdef ARDUINO_PLATFORM_SPI

SPI.begin ();

SPI.setClockDivider (SPI_CLOCK_DIV2);

SPI.setBitOrder (MSBFIRST);

SPI.setDataMode (SPI_MODE0);

#endif

#ifdef MSVC_PLATFORM_SPI

ChannelConfig channelConf; // konfigurazzjoni tal-kanal

Status FT_STATUS;

/ * kkonfigurat l-issi settings tal-ispi * /

channelConf.ClockRate = host-> hal_config.spi_clockrate_khz * 1000;

channelConf.LatencyTimer = 2;

channelConf.configOptions = SPI_CONFIG_OPTION_MODE0 | SPI_CONFIG_OPTION_CS_DBUS3 | SPI_CONFIG_OPTION_CS_ACTIVELOW;

channelConf.Pin = 0x00000000; / * FinalVal-FinalDir-InitVal-InitDir (għal dir 0 = ġewwa, 1 = barra) * /


/ * Iftaħ l-ewwel kanal disponibbli * /

SPI_OpenChannel (host-> hal_config.channel_no, (FT_HANDLE *) & host-> hal_handle);

status = SPI_InitChannel ((FT_HANDLE) host-> hal_handle, & channelConf);

printf ("handle = 0x% x status = 0x% x", host-> hal_handle, status);

#endif

host-> ft_cmd_fifo_wp = host-> ft_dl_buff_wp = 0;

host-> status = FT_GPU_HAL_OPENED;

ritorn VERU;

}

ft_void_t Ft_Gpu_Hal_Close (Ft_Gpu_Hal_Context_t * host)

{

host-> status = FT_GPU_HAL_CLOSED;

#ifdef MSVC_PLATFORM_SPI

/ * Agħlaq il-kanal * /

SPI_CloseChannel (host-> hal_handle);

#endif

#ifdef ARDUINO_PLATFORM_SPI

SPI.end ();

#endif

}

ft_void_t Ft_Gpu_Hal_DeInit ()

{

#ifdef MSVC_PLATFORM_SPI

// Naddaf il-MPSSE Lib

Cleanup_libMPSSE ();

#endif

}


/ * L-APIs għat-trasferiment tal-qari / kitba kontinwament biss b'sistema żgħira ta 'bafer * /

ft_void_t Ft_Gpu_Hal_StartTransfer (Ft_Gpu_Hal_Context_t * host, FT_GPU_TRANSFERDIR_T rw, ft_uint32_t addr)

{

jekk (FT_GPU_READ == rw) {


#ifdef MSVC_PLATFORM_SPI

ft_uint8_t Transfer_Array [4];

ft_uint32_t DaqsTrasferit;


/ * Ikteb il-pakkett li jinqara * /

Transfer_Array [0] = addr >> 16;

Transfer_Array [1] = addr >> 8;

Transfer_Array [2] = addr;


Transfer_Array [3] = 0; // byte Aqra manikin

SPI_Write ((FT_HANDLE) host-> hal_handle, Transfer_Array, sizeof (Transfer_Array), & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES | SPI_TRANSFER_OPTIONS_CHIPSELECT_ENABLE);

#endif

#ifdef ARDUINO_PLATFORM_SPI

digitalWrite (FT_ARDUINO_PRO_SPI_CS, LOW);

SPI.transfer (addr >> 16);

SPI.transfer (highByte (addr));

SPI.transfer (lowByte (addr));


SPI.transfer (0); // Byte Aqra Dummy

#endif

host-> status = FT_GPU_HAL_READING;

} else {

#ifdef MSVC_PLATFORM_SPI

ft_uint8_t Transfer_Array [3];

ft_uint32_t DaqsTrasferit;


/ * Ikteb il-pakkett li jinqara * /

Transfer_Array [0] = (0x80 | (addr >> 16));

Transfer_Array [1] = addr >> 8;

Transfer_Array [2] = addr;

SPI_Write ((FT_HANDLE) host-> hal_handle, Transfer_Array, 3, & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES | SPI_TRANSFER_OPTIONS_CHIPSELECT_ENABLE);

#endif

#ifdef ARDUINO_PLATFORM_SPI

digitalWrite (FT_ARDUINO_PRO_SPI_CS, LOW);

SPI.transfer (0x80 | (addr >> 16));

SPI.transfer (highByte (addr));

SPI.transfer (lowByte (addr));

#endif

host-> status = FT_GPU_HAL_WRITING;

}

}

/ * L-APIs għall-kitba ta 'trasferiment kontinwament biss * /

ft_void_t Ft_Gpu_Hal_StartCmdTransfer (Ft_Gpu_Hal_Context_t * host, FT_GPU_TRANSFERDIR_T rw, għadd ft_uint16_t)

{

Ft_Gpu_Hal_StartTransfer (host, rw, host-> ft_cmd_fifo_wp + RAM_CMD);

}


ft_uint8_t Ft_Gpu_Hal_TransferString (Ft_Gpu_Hal_Context_t * host, const ft_char8_t * string)

{

ft_uint16_t length = strlen (spag);

filwaqt li (tul -) {

Ft_Gpu_Hal_Transfer8 (host, * string);

spag ++;

}

// Ehmeż null wieħed bħala bandiera tat-tmiem

Ft_Gpu_Hal_Transfer8 (host, 0);

}

ft_uint8_t Ft_Gpu_Hal_Transfer8 (Ft_Gpu_Hal_Context_t * host, valur ft_uint8_t)

{

#ifdef ARDUINO_PLATFORM_SPI

return SPI.transfer (valur);

#endif

#ifdef MSVC_PLATFORM_SPI

ft_uint32_t DaqsTrasferit;

jekk (host-> status == FT_GPU_HAL_WRITING) {

SPI_Write (host-> hal_handle, & valur, sizeof (valur), & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

} else {

SPI_Read (host-> hal_handle, & valur, sizeof (valur), & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

}


if (SizeTrasferit! = sizeof (valur))

host-> status = FT_GPU_HAL_STATUS_ERROR;

valur tar-ritorn;

#endif

}


ft_uint16_t Ft_Gpu_Hal_Transfer16 (Ft_Gpu_Hal_Context_t * host, valur ft_uint16_t)

{

ft_uint16_t retVal = 0;


jekk (host-> status == FT_GPU_HAL_WRITING) {

Ft_Gpu_Hal_Transfer8 (host, valur & 0xFF); // LSB l-ewwel

Ft_Gpu_Hal_Transfer8 (host, (valur >> 8) & 0xFF);

} else {

retVal = Ft_Gpu_Hal_Transfer8 (host, 0);

retVal | = (ft_uint16_t) Ft_Gpu_Hal_Transfer8 (host, 0) <>

}


return retVal;

}

ft_uint32_t Ft_Gpu_Hal_Transfer32 (ospitanti Ft_Gpu_Hal_Context_t *, valur ft_uint32_t)

{

ft_uint32_t retVal = 0;

jekk (host-> status == FT_GPU_HAL_WRITING) {

Ft_Gpu_Hal_Transfer16 (host, valur & 0xFFFF); // LSB l-ewwel

Ft_Gpu_Hal_Transfer16 (host, (valur >> 16) & 0xFFFF);

} else {

retVal = Ft_Gpu_Hal_Transfer16 (ospitanti, 0);

retVal | = (ft_uint32_t) Ft_Gpu_Hal_Transfer16 (host, 0) <>

}

return retVal;

}


ft_void_t Ft_Gpu_Hal_EndTransfer (Ft_Gpu_Hal_Context_t * host)

{

#ifdef MSVC_PLATFORM_SPI

// żbilanċ biss is-CS - ibgħat 0 bytes b 'CS disable

SPI_ToggleCS ((FT_HANDLE) host-> hal_handle, FALSE);

#endif

#ifdef ARDUINO_PLATFORM_SPI

digitalWrite (FT_ARDUINO_PRO_SPI_CS, GĦOLJA);

#endif

host-> status = FT_GPU_HAL_OPENED;

}

ft_uint8_t Ft_Gpu_Hal_Rd8 (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr)

{

valur ft_uint8_t;

Ft_Gpu_Hal_StartTransfer (host, FT_GPU_READ, addr);

valur = Ft_Gpu_Hal_Transfer8 (host, 0);

Ft_Gpu_Hal_EndTransfer (host);

valur tar-ritorn;

}

ft_uint16_t Ft_Gpu_Hal_Rd16 (ospitanti Ft_Gpu_Hal_Context_t *, ft_uint32_t addr)

{

valur ft_uint16_t;

Ft_Gpu_Hal_StartTransfer (host, FT_GPU_READ, addr);

valur = Ft_Gpu_Hal_Transfer16 (host, 0);

Ft_Gpu_Hal_EndTransfer (host);

valur tar-ritorn;

}

ft_uint32_t Ft_Gpu_Hal_Rd32 (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr)

{

valur ft_uint32_t;

Ft_Gpu_Hal_StartTransfer (host, FT_GPU_READ, addr);

valur = Ft_Gpu_Hal_Transfer32 (host, 0);

Ft_Gpu_Hal_EndTransfer (host);

valur tar-ritorn;

}

ft_void_t Ft_Gpu_Hal_Wr8 (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr, ft_uint8_t v)

{

Ft_Gpu_Hal_StartTransfer (host, FT_GPU_WRITE, addr);

Ft_Gpu_Hal_Transfer8 (host, v);

Ft_Gpu_Hal_EndTransfer (host);

}

ft_void_t Ft_Gpu_Hal_Wr16 (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr, ft_uint16_t v)

{

Ft_Gpu_Hal_StartTransfer (host, FT_GPU_WRITE, addr);

Ft_Gpu_Hal_Transfer16 (host, v);

Ft_Gpu_Hal_EndTransfer (host);

}

ft_void_t Ft_Gpu_Hal_Wr32 (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr, ft_uint32_t v)

{

Ft_Gpu_Hal_StartTransfer (host, FT_GPU_WRITE, addr);

Ft_Gpu_Hal_Transfer32 (host, v);

Ft_Gpu_Hal_EndTransfer (host);

}

ft_void_t Ft_Gpu_HostCommand (Ft_Gpu_Hal_Context_t * host, ft_uint8_t cmd)

{

#ifdef MSVC_PLATFORM_SPI

ft_uint8_t Transfer_Array [3];

ft_uint32_t DaqsTrasferit;


Transfer_Array [0] = cmd;

Transfer_Array [1] = 0;

Transfer_Array [2] = 0;


SPI_Write (host-> hal_handle, Transfer_Array, sizeof (Transfer_Array), & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES | SPI_TRANSFER_OPTIONS_CHIPSELECT_ENABLE | SPI_TRANSFER_OPTIONS_CHIPS);

#endif

#ifdef ARDUINO_PLATFORM_SPI

digitalWrite (FT_ARDUINO_PRO_SPI_CS, LOW);

SPI.transfer (cmd);

SPI.transfer (0);

SPI.transfer (0);

digitalWrite (FT_ARDUINO_PRO_SPI_CS, GĦOLJA);

#endif

}

ft_void_t Ft_Gpu_ClockSelect (Ft_Gpu_Hal_Context_t * host, FT_GPU_PLL_SOURCE_T pllsource)

{

Ft_Gpu_HostCommand (host, pllsource);

}

ft_void_t Ft_Gpu_PLL_FreqSelect (Ft_Gpu_Hal_Context_t * host, FT_GPU_PLL_FREQ_T freq)

{

Ft_Gpu_HostCommand (host, freq);

}

ft_void_t Ft_Gpu_PowerModeSwitch (Ft_Gpu_Hal_Context_t * host, FT_GPU_POWER_MODE_T pwrmode)

{

Ft_Gpu_HostCommand (host, pwrmode);

}

ft_void_t Ft_Gpu_CoreReset (Ft_Gpu_Hal_Context_t * host)

{

Ft_Gpu_HostCommand (host, 0x68);

}

ft_void_t Ft_Gpu_Hal_Updatecmdfifo (Ft_Gpu_Hal_Context_t * host, ft_uint16_t għadd)

{

host-> ft_cmd_fifo_wp = (host-> ft_cmd_fifo_wp + għadd) & 4095;


// allinjament ta '4 byte

host-> ft_cmd_fifo_wp = (host-> ft_cmd_fifo_wp + 3) & 0xffc;

Ft_Gpu_Hal_Wr16 (ospitanti, REG_CMD_WRITE, host-> ft_cmd_fifo_wp);

}



ft_uint16_t Ft_Gpu_Cmdfifo_Freespace (Ft_Gpu_Hal_Context_t * host)

{

mili ft_uint16_t, ritval;


milja = (host-> ft_cmd_fifo_wp - Ft_Gpu_Hal_Rd16 (ospitanti, REG_CMD_READ)) & 4095;

retval = (FT_CMD_FIFO_SIZE - 4) - milja;

ritorn (revoka);

}

ft_void_t Ft_Gpu_Hal_WrCmdBuf (Ft_Gpu_Hal_Context_t * host, ft_uint8_t * buffer, ft_uint16_t għadd)

{

ft_uint32_t length = 0, SizeTransfered = 0;


#define MAX_CMD_FIFO_TRANSFER Ft_Gpu_Cmdfifo_Freespace (host)

tagħmel {

tul = għadd;

jekk (tul> MAX_CMD_FIFO_TRANSFER) {

tul = MAX_CMD_FIFO_TRANSFER;

}

Ft_Gpu_Hal_CheckCmdBuffer (host, length);


Ft_Gpu_Hal_StartCmdTransfer (host, FT_GPU_WRITE, tul);


#ifdef ARDUINO_PLATFORM_SPI

SizeTransfered = 0;

filwaqt li (it-tul--) {

Ft_Gpu_Hal_Transfer8 (host, * buffer);

buffer ++;

SizeTransfered ++;

}

length = Daqs Trasferit;

#endif

#ifdef MSVC_PLATFORM_SPI

{

SPI_Write (host-> hal_handle, buffer, length, & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

length = Daqs Trasferit;

buffer + = SizeTransfered;

}

#endif


Ft_Gpu_Hal_EndTransfer (host);

Ft_Gpu_Hal_Updatecmdfifo (host, length);


Ft_Gpu_Hal_WaitCmdfifo_empty (ospitanti);


count - = tul;

} filwaqt (għadd> 0);

}

ft_void_t Ft_Gpu_Hal_WrCmdBuf_nowait (Ft_Gpu_Hal_Context_t * host, ft_uint8_t * bafer, ft_uint16_t għadd)

{

ft_uint32_t length = 0, SizeTransfered = 0;


#define MAX_CMD_FIFO_TRANSFER Ft_Gpu_Cmdfifo_Freespace (host)


tagħmel {

tul = għadd;

jekk (tul> MAX_CMD_FIFO_TRANSFER) {

tul = MAX_CMD_FIFO_TRANSFER;

}

Ft_Gpu_Hal_CheckCmdBuffer (host, length);


Ft_Gpu_Hal_StartCmdTransfer (host, FT_GPU_WRITE, tul);


#ifdef ARDUINO_PLATFORM_SPI

SizeTransfered = 0;

filwaqt li (it-tul--) {

Ft_Gpu_Hal_Transfer8 (host, * buffer);

buffer ++;

SizeTransfered ++;

}

length = Daqs Trasferit;

#endif


#ifdef MSVC_PLATFORM_SPI

{

SPI_Write (host-> hal_handle, buffer, length, & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

length = Daqs Trasferit;

buffer + = SizeTransfered;

}

#endif


Ft_Gpu_Hal_EndTransfer (host);

Ft_Gpu_Hal_Updatecmdfifo (host, length);

count - = tul;

} filwaqt (għadd> 0);

}

#ifdef ARDUINO_PLATFORM_SPI

ft_void_t Ft_Gpu_Hal_WrCmdBufFromFlash (Ft_Gpu_Hal_Context_t * host, FT_PROGMEM ft_prog_uchar8_t * bafer, għadd ta 'ft_uint16_t)

{

ft_uint32_t length = 0, SizeTransfered = 0;


#define MAX_CMD_FIFO_TRANSFER Ft_Gpu_Cmdfifo_Freespace (host)

tagħmel {

tul = għadd;

jekk (tul> MAX_CMD_FIFO_TRANSFER) {

tul = MAX_CMD_FIFO_TRANSFER;

}

Ft_Gpu_Hal_CheckCmdBuffer (host, length);


Ft_Gpu_Hal_StartCmdTransfer (host, FT_GPU_WRITE, tul);



SizeTransfered = 0;

filwaqt li (it-tul--) {

Ft_Gpu_Hal_Transfer8 (host, ft_pgm_read_byte_near (buffer));

buffer ++;

SizeTransfered ++;

}

length = Daqs Trasferit;


Ft_Gpu_Hal_EndTransfer (host);

Ft_Gpu_Hal_Updatecmdfifo (host, length);


Ft_Gpu_Hal_WaitCmdfifo_empty (ospitanti);


count - = tul;

} filwaqt (għadd> 0);

}

#endif

ft_void_t Ft_Gpu_Hal_CheckCmdBuffer (Ft_Gpu_Hal_Context_t * host, ft_uint16_t għadd)

{

ft_uint16_t getfreespace;

tagħmel {

getfreespace = Ft_Gpu_Cmdfifo_Freespace (host);

} filwaqt (getfreespace <>

}

ft_void_t Ft_Gpu_Hal_WaitCmdfifo_empty (Ft_Gpu_Hal_Context_t * host)

{

waqt (Ft_Gpu_Hal_Rd16 (ospitanti, REG_CMD_READ) = Ft_Gpu_Hal_Rd16 (ospitanti, REG_CMD_WRITE));

host-> ft_cmd_fifo_wp = Ft_Gpu_Hal_Rd16 (ospitanti, REG_CMD_WRITE);

}


ft_uint8_t Ft_Gpu_Hal_WaitCmdfifo_empty_status (Ft_Gpu_Hal_Context_t * host)

{

jekk (Ft_Gpu_Hal_Rd16 (ospitanti, REG_CMD_READ)! = Ft_Gpu_Hal_Rd16 (ospitanti, REG_CMD_WRITE))

{

ritorn 0;

}

inkella

{

host-> ft_cmd_fifo_wp = Ft_Gpu_Hal_Rd16 (ospitanti, REG_CMD_WRITE);

ritorn 1;

}

}


ft_void_t Ft_Gpu_Hal_WaitLogo_Finish (Ft_Gpu_Hal_Context_t * host)

{

ft_int16_t cmdrdptr, cmdwrptr;


tagħmel {

cmdrdptr = Ft_Gpu_Hal_Rd16 (host, REG_CMD_READ);

cmdwrptr = Ft_Gpu_Hal_Rd16 (host, REG_CMD_WRITE);

} filwaqt ((cmdwrptr! = cmdrdptr) || (cmdrdptr! = 0));

host-> ft_cmd_fifo_wp = 0;

}



ft_void_t Ft_Gpu_Hal_ResetCmdFifo (ospitanti Ft_Gpu_Hal_Context_t *)

{

host-> ft_cmd_fifo_wp = 0;

}



ft_void_t Ft_Gpu_Hal_WrCmd32 (Ft_Gpu_Hal_Context_t * host, ft_uint32_t cmd)

{

Ft_Gpu_Hal_CheckCmdBuffer (host, sizeof (cmd));

Ft_Gpu_Hal_Wr32 (ospitanti, RAM_CMD + host-> ft_cmd_fifo_wp, cmd);

Ft_Gpu_Hal_Updatecmdfifo (host, sizeof (cmd));

}

ft_void_t Ft_Gpu_Hal_ResetDLBuffer (Ft_Gpu_Hal_Context_t * host)

{

host-> ft_dl_buff_wp = 0;

}

/ * Toggle PD_N pin tal-bord FT800 għal ċiklu ta 'enerġija

ft_void_t Ft_Gpu_Hal_Powercycle (ospitant Ft_Gpu_Hal_Context_t *, ft_bool_t up)

{

jekk (sa)

{

#ifdef MSVC_PLATFORM

FT_WriteGPIO (host-> hal_handle, 0xBB, 0x08); // PDN issettjat għal 0, qabbad il-wajer BLUE ta 'MPSSE ma' PDN # tal-bord FT800

Ft_Gpu_Hal_Sleep (20);


FT_WriteGPIO (host-> hal_handle, 0xBB, 0x88); // PDN issettjat għal 1

Ft_Gpu_Hal_Sleep (20);

#endif

#ifdef ARDUINO_PLATFORM

digitalWrite (FT800_PD_N, LOW);

Ft_Gpu_Hal_Sleep (20);


DigitalWrite (FT800_PD_N, GĦOLJA);

Ft_Gpu_Hal_Sleep (20);

#endif

} inkella

{

#ifdef MSVC_PLATFORM

FT_WriteGPIO (host-> hal_handle, 0xBB, 0x88); // PDN issettjat għal 1

Ft_Gpu_Hal_Sleep (20);

FT_WriteGPIO (host-> hal_handle, 0xBB, 0x08); // PDN issettjat għal 0, qabbad il-wajer BLUE ta 'MPSSE ma' PDN # tal-bord FT800

Ft_Gpu_Hal_Sleep (20);

#endif

#ifdef ARDUINO_PLATFORM

DigitalWrite (FT800_PD_N, GĦOLJA);

Ft_Gpu_Hal_Sleep (20);

digitalWrite (FT800_PD_N, LOW);

Ft_Gpu_Hal_Sleep (20);

#endif

}

}

ft_void_t Ft_Gpu_Hal_WrMemFromFlash (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr, const ft_prog_uchar8_t * bafer, ft_uint32_t tul)

{

ft_uint32_t SizeTransfered = 0;


Ft_Gpu_Hal_StartTransfer (host, FT_GPU_WRITE, addr);


#ifdef ARDUINO_PLATFORM

filwaqt li (it-tul--) {

Ft_Gpu_Hal_Transfer8 (host, ft_pgm_read_byte_near (buffer));

buffer ++;

}

#endif


#ifdef MSVC_PLATFORM_SPI

{

SPI_Write ((FT_HANDLE) host-> hal_handle, buffer, length, & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

}

#endif



Ft_Gpu_Hal_EndTransfer (host);

}


ft_void_t Ft_Gpu_Hal_WrMem (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr, const ft_uint8_t * bafer, ft_uint32_t tul)

{

ft_uint32_t SizeTransfered = 0;


Ft_Gpu_Hal_StartTransfer (host, FT_GPU_WRITE, addr);


#ifdef ARDUINO_PLATFORM

filwaqt li (it-tul--) {

Ft_Gpu_Hal_Transfer8 (host, * buffer);

buffer ++;

}

#endif


#ifdef MSVC_PLATFORM_SPI

{

SPI_Write ((FT_HANDLE) host-> hal_handle, buffer, length, & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

}

#endif



Ft_Gpu_Hal_EndTransfer (host);

}



ft_void_t Ft_Gpu_Hal_RdMem (Ft_Gpu_Hal_Context_t * host, ft_uint32_t addr, ft_uint8_t * bafer, ft_uint32_t tul)

{

ft_uint32_t SizeTransfered = 0;


Ft_Gpu_Hal_StartTransfer (host, FT_GPU_READ, addr);


#ifdef ARDUINO_PLATFORM

filwaqt li (it-tul--) {

* buffer = Ft_Gpu_Hal_Transfer8 (host, 0);

buffer ++;

}

#endif


#ifdef MSVC_PLATFORM_SPI

{

SPI_Read ((FT_HANDLE) host-> hal_handle, buffer, length, & SizeTransfered, SPI_TRANSFER_OPTIONS_SIZE_IN_BYTES);

}

#endif


Ft_Gpu_Hal_EndTransfer (host);

}


ft_int32_t Ft_Gpu_Hal_Dec2Ascii (ft_char8_t * pSrc, valur ft_int32_t)

{

ft_int16_t Tul;

ft_char8_t * pdst, charval;

ft_int32_t CurrVal = valur, tmpval, i;

ft_char8_t tmparray [16], idx = 0;


Tul = strlen (pSrc);

pdst = pSrc + Tul;


jekk (0 == valur)

{

* pdst ++ = '0';

* pdst ++ = '';

ritorn 0;

}


jekk (CurrVal <>

{

* pdst ++ = '-';

CurrVal = - CurrVal;

}

/ * daħħal il-valur * /

filwaqt (CurrVal> 0) {

tmpval = CurrVal;

CurrVal / = 10;

tmpval = tmpval - CurrVal * 10;

charval = '0' + tmpval;

tmparray [idx ++] = charval;

}


għal (i = 0; i

{

* pdst ++ = tmparray [idx-i-1];

}

* pdst ++ = '';


ritorn 0;

}


ft_void_t Ft_Gpu_Hal_Sleep (ft_uint16_t ms)

{

#ifdef MSVC_PLATFORM

Sleep (ms);

#endif

#ifdef ARDUINO_PLATFORM

dewmien (ms);

#endif

}